1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device provided with a bipolar transistor and a method of manufacturing the same.
2. Description of the Background Art
Bipolar transistors have been known as a kind of semiconductor devices. Bipolar transistors include npn (npn-type) bipolar transistors and pnp (pnp-type) bipolar transistors. The npn and pnp bipolar transistors may be arranged in a common semiconductor device. This kind of semiconductor device will be referred to as a xe2x80x9cbipolar IC (Integrated Circuit)xe2x80x9d hereinafter. The process of manufacturing the bipolar IC is executed based on the process of forming the npn bipolar transistor. Therefore, a structure shown in FIG. 28 is often used for producing the pnp bipolar transistor of a good performance in the bipolar IC. FIG. 28 is a schematic perspective view of a bipolar transistor IC which is an example of a conventional semiconductor device. Referring to FIG. 28, the conventional bipolar IC will now be described.
Referring to FIG. 28, the bipolar IC is provided with a pnp bipolar transistor and a npn bipolar transistor. In bipolar IC, n-type epitaxial layers 104a-104c, 104f-104h are formed on a pxe2x88x92-type substrate 101 by an epitaxial growth method. n+-type buried regions 102a and 102b are formed in the boundary region between pxe2x88x92-type substrate 101 and n-type epitaxial layers 104a-104c, 104f-104h. n+-type buried region 102a electrically isolates the pnp bipolar transistor from pxe2x88x92-type substrate 101. n+-type buried region 102b forms a low resistance portion in a collector region of the npn bipolar transistor.
A p-type buried region 103b is formed on n+-type buried region 102a. p-type buried region 103b operates as a collector region of the pnp bipolar transistor. The bipolar IC is further provided with p+-type diffusion regions 105b and 105c, which are in contact with p-type buried region 103b, and extend to the top surfaces, i.e., the main surfaces of n-type epitaxial layers 104a-104c, 104f-104h. p+-type diffusion regions 105b and 105c form a collector leader portion of the pnp bipolar transistor. An n-type epitaxial layer 104c is located in a region surrounded by p-type buried region 103b and p+-type diffusion regions 105b and 105c. n-type epitaxial layer 104c forms a base region of the pnp bipolar transistor. A p+-type diffusion region 106b serving as an emitter region of the pnp bipolar transistor is formed at the main surface of n-type epitaxial layer 104c. A p+-type diffusion region 106a is likewise formed in p+-type diffusion region 105b. This p+-type diffusion region 106a is provided for lowering the resistance of the collector leader portion of the pnp bipolar transistor. n-type epitaxial layer 104c is provided with an n+-type diffusion region 107a. n+-type diffusion region 107a is provided for lowering the base leader resistance. The pnp bipolar transistor is surrounded by n-type epitaxial layers 104b and 104f serving as an element isolating region.
An oxide film 108 is formed on the top surfaces of n-type epitaxial layers 104a-104c, 104f-104h. Oxide film 108 is provided with a contact hole 109a located above p+-type diffusion region 106a. In a region located above p+-type diffusion region 106b, oxide film 108 is provided with a contact hole 109b. In a region located above n+-type diffusion region 107a, oxide film 108 is provided with a contact hole 109c. 
Electrodes 110a-110c are formed on oxide film 108. Electrode 110a is electrically connected to p+-type diffusion region 106a through contact hole 109a. Electrode 110a serves as a collector leader electrode. Electrode 110b is electrically connected to p+-type diffusion region 106b through contact hole 109b. Electrode 110b serves as an emitter leader electrode. Electrode 110c is electrically connected to n+-type diffusion region 107a through contact hole 109c. Electrode 110c serves as a base leader electrode. The pnp bipolar transistor shown in FIG. 28 is of a vertical type, as can also be seen from FIG. 28.
In the region located above n+-type buried region 102b, a p+-type diffusion region 106c is formed at the top surface of n-type epitaxial layer 104g. n+-type buried region 102b forms a high resistance portion of the collector region of the npn bipolar transistor. An n+-type diffusion region 107c is formed at the top surface of p+-type diffusion region 106c. An n+-type diffusion region 107b is formed at the top surface of n-type epitaxial layer 104g. n-type epitaxial layer 104g serves as a high resistance portion of the collector region of the npn bipolar transistor. p+-type diffusion region 106c serves as a base region of the npn bipolar transistor. n+-type diffusion region 107c serves as an emitter region of the npn bipolar transistor. n+-type diffusion region 107b is provided for lowering the collector leader resistance of the npn bipolar transistor.
Oxide film 108 is formed on the top surface of n-type epitaxial layer 104g as already described. In a region located above n+-type diffusion regions 107b and 107c as well as p+-type diffusion region 106c, oxide film 108 is provided with contact holes 109d-109f. In regions located above contact holes 109d-109f, electrodes 110d-110f are formed on oxide film 108, respectively. Electrode 10d is connected to n+-type diffusion region 107b through contact hole 109d. This electrode 110d serves as a collector leader electrode. Electrode 110e is electrically connected to n+-type diffusion region 107c through contact hole 109e. Therefore, electrode 110e serves as an emitter leader electrode. Electrode 110f is electrically connected to p+-type diffusion region 106c through contact hole 109f. This electrode 110f serves as a base leader electrode. This npn bipolar transistor is surrounded by an element isolating region which is formed of p-type buried regions 103c and 103d as well as p+-type diffusion regions 105d and 105e. In a region opposed to the npn bipolar transistor with the pnp bipolar transistor therebetween, the bipolar IC is provided with an additional npn bipolar transistor, although not shown. The element isolating region formed of p-type buried region 103a and p+-type diffusion region 105a serves as the element isolating region for this additional npn bipolar transistor. n-type epitaxial layer 104a serves as a high resistance portion of the collector region of the above additional npn bipolar transistor. An additional npn bipolar transistor is formed in a position opposed to the pnp bipolar transistor with the npn bipolar transistor therebetween. n-type epitaxial layer 104h forms a high resistance portion of the collector region of this additional npn bipolar transistor.
Referring to FIGS. 29 to 32, description will now be made on the method of manufacturing the bipolar IC shown in FIG. 28. FIGS. 29 to 32 are schematic cross sections or schematic perspective views for showing the method of manufacturing the bipolar IC, which is an example of the conventional semiconductor device and is shown in FIG. 28.
As shown in FIG. 29, n+-type buried regions 102a and 102b are formed at the top surface of pxe2x88x92-type substrate 101. p-type buried regions 103a-103d are formed at predetermined regions of the top surface of pxe2x88x92-type substrate 101.
Then, an epitaxial method is conducted to from n-type epitaxial layer 104 (see FIG. 30) on the top surface of pxe2x88x92-type substrate 101. When conducting this epitaxial growth method, electrically conductive impurities diffuse from n+-type buried regions 102a and 102b as well as p-type buried regions 103a-103d into n-type epitaxial layer 104. A thermal oxide film 111 (see FIG. 30) is formed on the top surface of n-type epitaxial layer 104. In this manner, the structure shown in FIG. 30 is obtained.
In thermal oxide film 111, openings (not shown) are then formed in regions where p+-type diffusion regions 105a-105e (see FIG. 28), which will form the element isolation region and the collector leader portion, are to be formed. These openings may be formed in such a manner that a resist film covering a region other than the foregoing regions, in which the openings are to be formed, is formed by photolithography on the surface of thermal oxide film 11, and etching is effected on the thermal oxide film 111 masked with this resist film for removing portions thereof. p-type impurities are diffused into n-type epitaxial layer 104 through the above openings formed in thermal oxide film 111 so that p+-type diffusion regions 105a-105e (see FIG. 31) are formed. p+-type diffusion regions 105a-105e thus formed are in contact with p-type buried regions 103a-103d. Owing to provision of p+-type diffusion regions 105a-105e, n-type epitaxial layer 104 (see FIG. 30) is divided into n-type epitaxial layers 104a-104c, 104f-104h as shown in FIG. 31. After removing the thermal oxide film 111 by etching or the like, an oxide film 116 (see FIG. 31) is formed by the thermal oxidation method. Thereby, the structure shown in FIG. 31 is obtained.
Then, a resist film is formed on oxide film 116. Using this resist film as a mask, boron ions are implanted into predetermined regions so that p+-type diffusion regions 106a-106c (see FIG. 32) are formed. Thermal processing is executed after this implantation of boron ions.
Then, the oxide film 116 is partially removed to form openings (not shown) in regions where n+-type diffusion regions 107a-107c (see FIG. 32) are to be formed. n-type impurities are diffused through these openings into the predetermined regions in n-type epitaxial layers 104c and 104g as well as p+-type diffusion region 106c so that n+-type diffusion regions 107a-107c are formed. Thereafter, thermal processing is effected on n+-type diffusion regions 107a-107c. In this thermal processing, the top surfaces of n+-type diffusion regions 107a-107c within the openings formed in oxide film 116 are thermally oxidized to form thermal oxide films. As a result, the whole surface of the substrate is covered with an oxide film 117 as shown in FIG. 32.
An oxide film doped with phosphorus is formed as a protective film on oxide film 117 by a CVD (Chemical Vapor Deposition) method or the like. This oxide film formed by the CVD method and oxide film 117 form oxide film 108 (see FIG. 28).
Thereafter, contact holes 109a-109f are formed in predetermined regions of oxide film 108. Contact holes 109d, 109e and 109f are a collector contact, an emitter contact and a base contact in the npn bipolar transistor, respectively. In the pnp bipolar transistor, contact holes 109a-109c are a collector contact, an emitter contact and a base contact, respectively. Thereafter, electrodes 110a-110f, which are made of metal such as aluminum and serve as interconnection layers, are formed on oxide film 108. In this manner, the structure shown in FIG. 28 is formed.
In the case where the foregoing bipolar transistor is used in an output portion of a semiconductor device, the emitter, base and collector forming the bipolar transistor must have large sizes because a large current must flow through the output portion. More specifically, the contact area of each of the emitter region, base region and collector region must be large so that a large current can flow. For this purpose, as shown in FIG. 33, such measures are employed that the plurality of emitter regions, base regions and collector regions are arranged in parallel. FIG. 33 is a schematic perspective view showing another example of the conventional semiconductor device provided with a vertical pnp bipolar transistor, which is formed of a structure having a current drive capability corresponding to three transistors.
The example of the conventional semiconductor device shown in FIG. 33 will now be described.
Referring to FIG. 33, the semiconductor device is provided with n-type epitaxial layers 104a-104g on pxe2x88x92-type substrate 101, similarly to the semiconductor device shown in FIG. 28. n+-type buried region 102 and p-type buried regions 103a and 103c are formed in a boundary region between pxe2x88x92-type substrate 101 and n-type epitaxial layers 104a-104g. n+-type buried region 102 electrically isolates the pnp bipolar transistor from pxe2x88x92-type substrate 101. p-type buried region 103b is formed on n+-type buried region 102. p-type buried region 103b serves as a collector region of the pnp bipolar transistor. p+-type diffusion regions 105b-105e serving as the collector leader portion is formed in the predetermined region on p-type buried region 103b. p+-type diffusion regions 105b-105e and p-type buried region 103b surround n-type epitaxial layers 104c-104e. n-type epitaxial layers 104b and 104f serving as the element isolating region of the pnp bipolar transistor surround p-type buried region 103b. p+-type diffusion regions 105a and 105f surrounding p-type buried region 103b are formed in the regions located above p-type buried regions 103a and 103c, respectively. p-type buried regions 103a and 103c as well as p+-type diffusion regions 105a and 105f form the element isolation of an npn bipolar transistor (not shown). n-type epitaxial layers 104a and 104g form a high resistance portion of the collector region of this unillustrated npn bipolar transistor.
p+-type diffusion regions 106b, 106d and 106f as well as n+-type diffusion regions 107a-107c are formed in predetermined regions in n-type epitaxial layers 104c-104e. n-type epitaxial layers 104c-104e serve as the base region of the pnp bipolar transistor. p+-type diffusion regions 106b, 106d and 106f serve as the emitter region of the pnp bipolar transistor. n+-type diffusion regions 107a-107c have a function of lowering the leading resistance of the base region of the pnp bipolar transistor.
In p+-type diffusion regions 105b-105e, there are formed p+-type diffusion regions 106a, 106c, 106e and 106g, which have a function of lowering a leader resistance of the collector.
An oxide film 108 is formed on the top surfaces of n-type epitaxial layers 104a-104g. Oxide film 108 is provided at predetermined regions with contact holes 109a-109j, respectively. Contact holes 109a, 109d, 109g and 109j are collector contacts. Contact holes 109b, 109e, 109h are emitter contacts. Contact holes 109c, 109f and 109i are base contacts. Electrodes 110a-110j made of metal such as aluminum have portions located in contact holes 109a-109j, respectively, and extend therefrom onto the top surface of oxide film 108. Electrodes 110a, 110d, 110g and 110j are collector leader electrodes. Electrodes 110b, 110e and 110h are emitter leader electrodes, and electrodes 110c, 110f and 110i are base leader electrodes.
FIGS. 34 and 35 are schematic perspective views showing another example of the method of manufacturing the conventional semiconductor device shown in FIG. 33. Referring to FIGS. 34 and 35, description will now be made on the method of manufacturing the bipolar IC which is an example of the semiconductor device, and is shown in FIG. 33. The method of manufacturing the semiconductor device shown in FIG. 33 is basically similar to the method of manufacturing the semiconductor device shown in FIGS. 29 to 32. Thus, processing is performed to from n+-type buried region 102 (see FIG. 34) at the main surface of pxe2x88x92-type substrate 101 (shown in FIG. 34). Then, p-type buried regions 103a-103c (see FIG. 34) are formed at the main surface of pxe2x88x92-type substrate 101. An epitaxial growth method is conducted to form the n-type epitaxial layer (not shown) on the main surface of pxe2x88x92-type substrate 101. Thereafter, thermal oxidation is conducted to form a thermal oxide film (not shown) on the top surface of the n-type epitaxial layer, similarly to the step shown in FIG. 30.
The thermal oxide film is partially removed to form openings (not shown). p-type impurities are diffused into predetermined regions of the n-type epitaxial layer through the openings so that p+-type diffusion regions 105a-105f (see FIG. 34) are formed. p-type buried regions 103a and 103c as well as p+-type diffusion regions 105a-105f divide the n-type epitaxial layer into n-type epitaxial layers 104a-104g (see FIG. 34). After forming p+-type diffusion regions 105a-105f, the thermal oxide film is once removed. The thermal oxidation method is executed again to form oxide film 116 (see FIG. 34) on the upper surfaces of n-type epitaxial layers 104a-104g. In these manners, the structure shown in FIG. 34 is obtained.
Thereafter, a resist film is formed on oxide film 116. Using this resist film as a mask, boron ions are implanted into the predetermined region, and then the thermal oxidation is performed. In this manner, p+-type diffusion regions 106a-106g (see FIG. 35) are formed. Thereafter, the resist film is removed. Oxide film 116 is partially removed from portions located on the regions where n+-type diffusion regions 107a-107c (see FIG. 35) are to be formed. Thereby, openings are formed. Through these openings, n-type impurities are diffused into the predetermined regions of n-type epitaxial layers 104c-104e so that n+-type diffusion regions 107a-107c are formed. Thermal oxidation processing is performed simultaneously with the thermal processing, which is performed for activating n+-type diffusion regions 107a-107c, so that thermal oxide films are formed in the foregoing openings, respectively. In this manner, the top surfaces of n-type epitaxial layers 104a-104g are covered with oxide film 117 (see FIG. 35). Thereby, the structure shown in FIG. 35 is obtained.
Using oxide film 117 as a protective film, the CVD method or the like is then conducted to form an oxide film doped with phosphorus. As a result, the oxide film doped with phosphorus and oxide film 117 form oxide film 108 (see FIG. 33).
Thereafter, contact holes 109a-109j are formed in predetermined regions of oxide film 108 through steps similar to those shown in FIGS. 29 to 32. Electrodes 110a-110j are formed on contact holes 109a-109j. In this manner, the structure shown in FIG. 33 is obtained.
In the semiconductor device shown in FIG. 33, the pnp bipolar transistor for output is provided with the plurality of emitter regions, base regions and collector regions, which are formed in parallel, for increasing the current drive capability. Therefore, the pnp bipolar transistor occupies a large area on the substrate.
p+-type diffusion regions 105b-105e serving as the collector leader portion are formed by diffusing the p-type conductive impurities into the n-type epitaxial layer as described above. When the conductive impurities diffuses to a predetermined depth, they also diffuse laterally. Therefore, the area occupied by the bipolar transistor can be reduced only to a limited extent.
However, further miniaturization and increase in density of the semiconductor device have been increasingly demanded. In the bipolar transistor for the output described above, therefore, it is strongly required to reduce an occupied area while maintaining a required value of the current drive capability.
An object of the invention is to provide a semiconductor device allowing reduction in area occupied by a bipolar transistor as well as a method of manufacturing the same.
Another object of the invention is to provide a semiconductor device, which can reliably keep a sufficient current drive capability while reducing an area occupied by a bipolar transistor, as well as a method of manufacturing the same.
According to an aspect of the invention, a semiconductor device includes a substrate, a first conductivity type region, a collector region, a base region and an emitter region. The first conductivity type region is formed on the substrate, and has a main surface. The collector region is formed in the first conductivity type region. The base region is located in the first conductivity type region and on the collector region. The emitter region is located in the first conductivity type region and on the base region. The first conductivity type region is provided with a groove extending from the main surface of the first conductivity type region to the collector region, and an isolation groove disposed around a vertical bipolar transistor including the collector, base and emitter regions. The groove is filled with a conductor of the second conductivity type. The isolation groove is filled with an isolation conductor of the second conductivity type.
In the prior art, a collector leader region is formed by diffusing impurities of the second conductivity type into the first conductivity type region. When diffusing the impurities of the second conductivity type to a predetermined depth, the impurities of the second conductivity type also diffuse and expand laterally. Therefore, the area occupied by the vertical bipolar transistor can be reduced only to a limited extent. According to the invention, however, the groove for the collector leader region is formed in the first conductivity type region, and the groove is filled with this conductor. Thereby, the width of the groove can be sufficiently reduced so that the width of the collector leader region can be reliably reduced as compared with the case where the collector leader region is formed by diffusing the impurities. As a result, the area occupied by the vertical bipolar transistor can be reduced. Accordingly, the sizes of the semiconductor device can be easily reduced.
By utilizing the isolation groove for element isolation, the width of element isolation can be reduced as compared with the conventional case where the element isolation is formed by the diffusing step. Therefore, the area occupied by the element isolation can be reduced so that the sizes of the semiconductor device can be further reduced.
The semiconductor device of the above aspect may include an additional collector region of the second conductivity type, an additional base region of the first conductivity type and an additional emitter region of the second conductivity type. The additional collector region may be formed in a region surrounded by the isolation groove in the first conductivity type region, and the additional base region may be located in the first conductivity type region and on the additional collector region. The additional emitter region may be located in the first conductivity type region and on the additional base region. The first conductivity type region may be provided with an additional groove extending from the main surface of the first conductivity type region to the additional collector region. The additional groove may be filled with an additional conductor of the second conductivity type.
In the above case, the plurality of collector regions, base regions and emitter regions are disposed in the region surrounded by the isolation groove, whereby it is possible and easy to provide the semiconductor device which includes the bipolar transistor having a high current drive capability. The additional conductor filling the additional groove is used as an additional collector leader region connected to the additional collector region, whereby the width of the additional collector leader region can be smaller than that in the prior art. Therefore, the area occupied by the bipolar transistor can be reliably reduced, and further the current drive capability can be high.
According to another aspect of the invention, a semiconductor device includes a substrate, a first conductivity type region, a collector region of a second conductivity type, a base region of a first conductivity type, an emitter region of the second conductivity type and a base leader electrode. The first conductivity type region is formed on the substrate, and has a main surface. The collector region is formed at the main surface of the first conductivity type region. The base region is disposed in the first conductivity type region, and neighbors to a periphery of the collector region. The emitter region is located in the first conductivity type region and is formed in a region opposed to the collector region with the base region therebetween. The base leader electrode is located in the first conductivity type region, and is formed in a region opposed to the emitter region with the collector region therebetween. A bipolar transistor including the collector, base and emitter regions is a lateral bipolar transistor. The collector region includes an impurity diffusion region of the second conductivity type formed at the main surface of the first conductivity type region, and a collector buried layer of the second conductivity type in contact with the lower side of the impurity diffusion region.
According to the above aspect, the collector buried region can be formed in the region deep from the main surface of the first conductivity type region, and such deep region cannot be reached in a general diffusion step without difficulty. It is possible to utilize, as the collector region, the collector buried layer of the second conductivity type, which is formed in the region deep from the main surface of the first conductivity type region. Therefore, the collector resistance can be smaller than that in the prior art. Therefore, the current drive capability of the bipolar transistor can be increased.
The base leader electrode is formed in the region opposed to the emitter region with the collector region therebetween. As a result, the lateral bipolar transistor includes the base leader electrode formed in a portion other than the portion between the collector and emitter regions. Consequently, in the semiconductor device employing the plurality of collector regions, base regions and emitter regions for achieving a further increased current drive capability, the base leader electrode which can be commonly utilized by the plurality of base regions can be formed in the region other than the portion between the collector and emitter regions. Therefore, the base leader electrode can be smaller in number than the plurality of base regions. Consequently, the area occupied by the bipolar transistor can be smaller than that in a conventional structure which employs base leader electrodes corresponding to the respective base regions.
In the semiconductor device of the above aspect, the collector region is preferably provided with a groove extending from the main surface of the first conductivity type region to the collector buried layer, and the impurity diffusion region preferably includes a conductor of the second conductivity type filling the groove.
According to the above structure, the width of the groove can be sufficiently reduced, whereby the width of the collector region can be reliably reduced as compared with the case where the collector region is formed by diffusing the impurities. As a result, the area occupied by the lateral bipolar transistor can be reduced. Accordingly, the sizes of the semiconductor device can be easily reduced.
In the semiconductor device of the above aspect, the emitter region is preferably provided with an additional groove formed at the main surface of the first conductivity type region, and preferably includes an additional conductor of the second conductivity type filling the additional groove.
In this case, since the conductor filling the additional groove is utilized as the emitter region, the width of the emitter region can be smaller than that of a conventional emitter region formed in the diffusion step. As a result, the area occupied by the bipolar transistor can be reduced.
In the semiconductor device of the above aspect, the emitter region preferably includes an additional impurity diffusion region of the second conductivity type reaching the main surface of the first conductivity type region, and an emitter buried layer of the second conductivity type in contact with the lower side of the additional impurity diffusion region.
According to the above aspect, the emitter buried region can be formed in the region, which is deep from the main surface of the first conductivity type region, and cannot be reached in a general diffusion step without difficulty. Since the emitter buried layer is utilized as the emitter region, the contact area between the emitter region and the base region can be further increased. Consequently, the current drive capability of the bipolar transistor can be further increased.
In the semiconductor device of the above aspect, the emitter region is preferably provided with an additional groove extending from the main surface of the first conductivity type region to the emitter buried layer, and the additional impurity diffusion region preferably includes an additional conductor of the second conductivity type filling the additional groove.
In this case, since the conductor filling the additional groove is utilized as the emitter region, the width of the emitter region can be smaller than that of the conventional emitter region formed in the diffusion step. Consequently, the area occupied by the bipolar transistor can be further reduced.
In the semiconductor device of the above aspect, the collector buried layer may be located at a lower level than the emitter region viewed from the main surface of the first conductivity type region, and may extend to a region other than the region located immediately under the emitter region.
In this case, since the collector buried layer has the extended form, the surface area of the collector buried layer can be large (and thus the contact area between the collector and base regions can be large) so that the collector resistance can be reduced. Consequently, the current drive capability can be further increased.
Since the collector buried layer is not present immediately under the emitter region, a breakdown voltage between the collector and emitter can be larger than that in the case where the collector buried layer extends immediately under the emitter region.
In the semiconductor device of the above aspect, the collector buried layer may be located at a lower level than the emitter region viewed from the main surface of the first conductivity type region, and may extend to a region located immediately under the emitter region.
In this case, since the collector buried layer extends to the position immediately under the emitter region, the bipolar transistor including these emitter, collector and base regions can perform an operation similar to that of a vertical bipolar transistor. As a result, the current drive capability similar to that of the conventional vertical bipolar transistor can be obtained.
Preferably, the semiconductor device of the above aspect further includes an additional collector region of the second conductivity type, an additional base region of the first conductivity type, an additional emitter region of the second conductivity type and a lower level buried layer of the first conductivity type. The additional collector region is formed at the main surface of the first conductivity type region. The additional base region is located in the first conductivity type region, and neighbors to the additional collector region. The additional emitter region is located in the first conductivity type region, and is formed in a region opposed to the additional collector region with the additional base region therebetween. An additional bipolar transistor including the additional collector region, the additional base region and the additional emitter region is a lateral bipolar transistor. The lower level buried layer is formed under the collector buried layer, and is connected to the base region and the additional base region. The base leader electrode is formed at the main surface of the first conductivity type region, and is electrically connected to the lower level buried layer.
In this case, the base leader electrode can operate as the base leader electrode common to the base region and the additional base region. As a result, the base leader electrode can be smaller in number than the base regions in the structure provided with the plurality of emitter regions, base regions and collector regions. Consequently, the area occupied by the bipolar transistor can be smaller than that in the conventional structure where the base leader electrodes are formed corresponding to the respective base regions.
According to still another aspect of the invention, the semiconductor device includes a substrate, a first conductivity type region, a collector region of a second conductivity type, a base region of a first conductivity type, an emitter region of the second conductivity type, and a base leader electrode. The first conductivity type region is formed on the substrate, and has a main surface. The collector region is formed at the main surface of the first conductivity type region. The base region is located in the first conductivity type region, and neighbors to the periphery of the collector region. The emitter region is located in the first conductivity type region, and is formed in a region opposed to the collector region with the base region therebetween. The base leader electrode is located in the first conductivity type region, and is formed in a region opposed to the emitter region with the collector region therebetween. A bipolar transistor including the collector, base and emitter regions is a lateral bipolar transistor. The collector region includes a conductor of the second conductivity type filling a groove formed at the main surface of the first conductivity type region, and an impurity diffusion layer of the second conductivity type formed around the groove.
In the above structure, since the conductor filling the groove and the impurity diffusion layer formed around the groove can be utilized as the collector region, the area occupied by the collector region can be smaller than that occupied by a conventional collector region formed in the diffusion step. As a result, an area occupied by the bipolar transistor can be reduced, and therefore the sizes of the semiconductor device can be easily reduced.
The base leader electrode is formed in the region opposed to the emitter region with the collector region therebetween. In this structure, the lateral bipolar transistor includes the base leader electrode formed in a portion other than the portion between the collector and emitter regions. Consequently, in the semiconductor device employing the plurality of collector regions, base regions and emitter regions for achieving a further increased current drive capability, the base leader electrode which can be commonly utilized by the plurality of base regions can be formed in the region other than the portion between the collector and emitter regions. Therefore, the base leader electrode can be smaller in number than the plurality of base regions. Consequently, the area occupied by the bipolar transistor can be smaller than that in a conventional structure which employs base leader electrodes corresponding to the respective base regions.
In the semiconductor device of the above aspect, a buried layer of the first conductivity type located under the collector region may be formed in the first conductivity type region, and may be in contact with the buried layer.
In this case, since the collector region extends to a deep region provided with the buried layer, the surface area of the collector region can be increased. As a result, a high current drive capability can be achieved in the bipolar transistor.
In the above case, the base region located between the emitter and collector regions can be electrically connected to the base leader electrode via the buried layer of the first conductivity type. The concentration of the first conductivity type impurities in the buried layer of the first conductivity type may be sufficiently increased, whereby the base leader resistance can be reduced.
In the semiconductor device of the above aspect, the emitter region may be in contact with the buried layer.
In this case, since the emitter region is likewise extended to a deep region in contact with the buried layer, the emitter region can have a large surface area. As a result, the current drive capability can be improved.
In the semiconductor device of the above aspect, the emitter region is preferably provided with an additional groove formed at the main surface of the first conductivity type region. The emitter region preferably includes an additional conductor of the second conductivity type filling the additional groove and an additional impurity diffusion layer of the second conductivity type formed around the additional groove.
Similarly to the collector region, the area occupied by the emitter region can be smaller than that occupied by the conventional emitter region formed in the diffusion step. Consequently, the area occupied by the bipolar transistor can be reduced.
According to a further aspect of the invention, a method of manufacturing a semiconductor device includes the following steps. A base buried layer of a first conductivity type is formed at a top surface of a substrate. A buried layer containing impurities of a second conductivity type is formed on the base buried layer. A first conductivity type region is formed on the top surface of the substrate by an epitaxial growth method, and a collector region is formed by diffusion of impurities of the second conductive type from the buried layer into the first conductivity type region. A groove reaching the collector region and an isolation groove disposed around the collector region are formed at the top surface of the first conductivity type region. The groove and the isolation groove in the first conductivity type region are filled with a conductor of the second conductivity type. Impurities of the second conductivity type are introduced into a region located within the first conductivity type region and spaced from the groove to form an emitter region of the second conductivity type.
According to the above method, the conductor filling the groove can be utilized as the collector leader region. By filling the groove and the isolation groove with the conductor of the second conductivity type, it is possible to form easily the collector leader region and the isolation structure occupying a smaller area that a collector leader region and an isolation structure formed in the conventional diffusion step. As a result, an area occupied by the bipolar transistor can be reduced.
In further another aspect, a method of manufacturing a semiconductor device includes the following steps. A base buried layer of a first conductivity type is formed at a top surface of a substrate. A buried layer containing impurities of a second conductivity type is formed in the base buried layer. A first conductivity type region is formed on the top surface of the substrate by an epitaxial growth method, and a collector buried layer of the second conductivity type forming a collector region is formed by diffusion of impurities of the second conductive type from the buried layer into the first conductivity type region. An impurity diffusion region of the second conductivity type forming the collector region is formed in a region extending from the top surface of the first conductivity type region to the collector buried layer. Impurities of the second conductivity type are introduced into a region located within the first conductivity type region and spaced from the impurity diffusion region to form an emitter region of the second conductivity type.
In the above aspect, since the collector buried layer is utilized as the collector region, the collector region can have an increased surface area. As a result, the semiconductor device provided with the bipolar transistor having an increased current drive capability can be easily obtained.
In yet another aspect, a method of manufacturing a semiconductor device includes the following steps. A buried layer containing impurities of a first conductivity type is formed at a top surface of a substrate. A first conductivity type region is formed on the top surface of the substrate by an epitaxial growth method, and a lower level buried layer is formed by diffusion of impurities of the first conductive type from the buried layer into the first conductivity type region. A groove is formed at the top surface of the first conductivity type region. The groove in the first conductivity type region is filled a conductor of the second conductivity type forming a collector region. An impurity diffusion region of the second conductivity type forming the collector region is formed around the groove in the first conductivity type region. Impurities of the second conductivity type are introduced into a region located within the first conductivity type region and spaced from the groove to form an emitter region of the second conductivity type.
In the above aspect, the conductor of the second conductivity type filling the groove and the impurity diffusion region can be utilized as the collector region. The collector region utilizing the above groove can have a width smaller than that of a collector region formed in the conventional diffusion step without difficulty. As a result, an area occupied by the bipolar transistor can be reliably reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.